FIG. 1 depicts a small portion of a conventional magnetic random access memory (MRAM) 1. The conventional MRAM 1 includes a magnetic storage cell 10 having a conventional magnetic element 12 that is typically a conventional magnetic tunneling junction (MTJ) 12, and a conventional selection device 14 that is typically an NMOS transistor 14. Also depicted are a conventional read word line 16, a conventional bit line 18, a conventional source line 20, and a conventional write word line 22. Data are stored in the conventional magnetic element 12 by programming the conventional magnetic element to be in a high resistance state or a low resistance state. Typically, a high resistance corresponds to a logical “1” and a low resistance corresponds to a logical “0”. However, it is possible that the low resistance could correspond to the logical “1” while the high resistance corresponds to a logical “0”. The transistor 14 is used as a “select device” for the read operation.
In order to write to the conventional magnetic memory cell 10, a magnetic field is typically used. This magnetic field (switching field) is sufficient to switch the conventional MTJ 12 between the high and low resistance states. Thus programming is typically performed by applying magnetic fields from current pulses flowing in both the bit line 18 and the write word line 22. In general, the magnetic field generated by current flowing in either the bit line 18 or the write word line 22 alone is insufficient to program the conventional magnetic element 12. However, in combination the bit line 18 and the write word line 22 generate the switching field at their cross point, the location of the conventional MTJ 12. The state to which the conventional MTJ 12 is written depends on the direction of the current flow through the conventional bit line 18 and conventional write word line 22.
The conventional magnetic element 12 is read by activating the selection transistor 14 using the read word line 16 and driving a read current through the conventional magnetic element using the corresponding bit line 18. In a memory array, only the conventional MTJ 12 at the cross point between the selected bit line 18 and the selected read word line 16 has current driven through it. Consequently, only this MTJ 12 is read. The magnitude of the read current through the selected bit line 18 depends upon the state (resistance) of the conventional MTJ 12. The read current through the conventional MTJ 12 is compared with that of the reference cell by a differential current sensor amplifier, as shown in FIG. 2, which produces different outputs for the states “1” and ‘0”.
FIG. 2 depicts a larger portion of a conventional MRAM array 30 that utilizes conventional magnetic memory cells such as the conventional memory cell 10 depicted in FIG. 1. Referring back to FIG. 2, the conventional magnetic storage cells 10 are arranged in rows and columns. Each conventional magnetic memory cell 10 is still associated with conventional bit lines 36 (corresponding to bit lines 18), conventional read word lines 34 (corresponding to read word line 16) and conventional write word lines 32. Also depicted are a conventional word line decoders/drivers 44, conventional digit line (write word line) selectors 40 and 42, a conventional bit line and ground line selector 50, a conventional bit line selector 52, a conventional differential current sensor amplifier 46, a reference column 38, a voltage supply/ground 48, and conventional transistors 51, 53, and 55. The read word lines 34 are connected to and enabled by the conventional word line decoders/drivers 44. Each write word line 32 may also be controlled by the conventional digit line selectors 40 and 42. The conventional bit lines 36 are connected to the conventional bit line selector 52 and the conventional bit and ground line selector 50. The conventional digit line selector 40, conventional bit line selector 52, and conventional bit and ground line selector 50 are connected to the gates of MOS transistors 51, 53, and 55. The transistors 51, 53, and 55 act as switches that connect the bit lines 36 and write word lines 32 to the power supply or ground. Consequently, the current flow in conventional bit line 36 and conventional write word line 32 is controlled during the write operations. The conventional word line decoders/drivers 44 and the bit line and ground line selector 50 control the read operations.
The conventional MRAM is programmed and read in a similar manner to the single magnetic memory cell 10 described above. During a program, or write operation, a bit line 36 is activated and carries a current that generates a portion of the switching field for the conventional MTJ 12. In addition, a corresponding write word line 32 is activated and carries a current that generates a remaining portion of the switching field. In most conventional MRAM 30, neither the magnetic field generated using the bit line 36, nor the magnetic field generated by the write word line 32 is alone sufficient to program, or switch the state of, any conventional magnetic element 12. However, in combination the bit line 36 and the write word line 32 can generate the switching field at their cross point. Consequently, a selected conventional magnetic element 12 can be written.
During a read operation, a read word line 34 and a corresponding bit line 36 containing the magnetic element to be read are activated. Only the conventional magnetic storage cell 10 at the cross point between the activated bit line 36 and the activated read word line 34 has current driven through it and, therefore, read. The resistance state of the conventional magnetic storage cell being read is compared to the reference cell 10′ using the differential current sensor 46, which compares the two current signals and produces an output Vout for memory state “1” or ‘0”.
Although the conventional magnetic storage cell 10 and the conventional MRAM 30 function, one of ordinary skill in the art will readily recognize that there are drawbacks. These drawbacks may be particularly severe for higher memory densities. The write operation depends upon magnetic fields generated by current driven through the corresponding bit lines 18/36 and write word lines 22/32. These magnetic fields are not a localized phenomenon. Consequently, the magnetic fields may affect other nearby conventional memory cells 10. In addition, a relatively large current corresponding to a relatively large magnetic field is used to write the conventional MTJ 12. Consequently, the conventional magnetic memory cells 10 that are not selected for writing may be disturbed or inadvertently written. Although this problem may be solved by using an advanced architecture called toggle writing, toggle writing raises different issues. Typically, toggle writing utilizes much higher magnetic field and, therefore, a significantly higher current. Thus, power consumption is greatly increased, which is undesirable. Moreover, toggle writing typically requires a read verification prior to actual writing. A total access time is, therefore, longer. This greater access time also makes toggle writing unattractive for high speed applications. In addition the above concerns, the current generation memory cell size for conventional a MRAM 30 that utilizes toggle writing is close to 40 f2, where f is the lithographic critical dimension. Although this size range is competitive with semiconductor memory SRAM, MRAM typically requires five to seven more masks for fabrication. As a result, the conventional MRAM may cost more than SRAM.
Accordingly, what is desired is a method and system for providing and utilizing magnetic memory cells which mitigates or eliminates the issues related memory cells employing spin transfer based switching with a reduced possibility of inducing dielectric breakdown in the conventional magnetic element 12. The present invention addresses such a need.